Hi All,

I seem to have a problem with stale data. Here is what I am doing

static volatile char test

:
:

(Interrupt handler)
test ++;


(main function)
test=0
print test
generate interrupt
print test
print test

What I get is
1st print: 0
2nd print: 0
3rd print: 1
I am developing on an lpc 2109. what I find odd is that the chip does ot have an onboard cache so it seems that the data is being cached some where. How should I get around this? Does FreeRTOS do such caching and if so how do i flush it?

I did consider the pipeline issue with arm but after running through a dew nops i still go the same result.

What do you guys think the issue is?

Thanks,
Colin

FreeRTOS cannot have any effect on execution order on a processor without a cache. Put break points on the various parts of code that set or read the test variable to determine the actual order that things are happening in. Maybe the interrupt is not executing when you think.

What happens if you generate more interrupts, is the count always one less than you expect? Are you initializing the test variable to 0?

Hi David,

Thanks for the reply. what was happening was I was using a binary semaphore to delay the task while waiting for the interrupt. However when i created the semaphore, I did not take it. Therefore when I called a take, the semaphore was already available and gave it to me straight away.

Thanks for the help.

Colin