Hi to all,
i have a big problem: i'm using a queue system to synchronize a task with 2 ISR (one from ethernet and one from timer).ISR unblock task with a binary semaphore. Inside ISR i'm using a queue to create events to insert into it(with xQueueSendFromISR function) and in the task i have a loop blocked with a xSemaphoreTake.Idon't understand why i have a bus fault when i execute the instruction xSemaphoreTake. Thanks in advice for your answer,

Alessio

Which architecture are you using? Are you basing your project on a provided demo? Have you created the semaphore and the queue before you use them (especially if the interrupt is executing before the scheduler is started)? Is anything working?

If it was created as a semaphore, then the ISR should use xSemaphoreGiveFromISR not xQueueSendFromISR, while Semaphores are built on Queue code, I don't think they are interchangeable (for instance, Semaphores set up the queue for a zero byte object, and the QueueSend may not be set up to handle something like that.

i'm using a STM32 architecture with Cortex M3 processor. I creathed both semaphore and queue before enable interrupts.I'm using a queue to simulate a producer-consumer model.Everytime i have an interrupt i insert an element in the queue,after i unblock task that consume elements in the queue. About ISR first i must insert an element on the queue (and i do it with xQueueSendFromISR) and after i do xSemaphoreGiveFromISR and finally before leave ISR i do portEND_SWITCHING_ISR.

Are you totally 100% sure that the priority of the interrupt is equal to or low than configMAX_SYSCALL_INTERRUPT_PRIORITY? On the STM32 for the priority to be lower the value of the priority must be higher (0 is the highest priority and 255 is the lowest priority, so if you don't set the priority it will be 0 by default and therefore the highest possible and this will cause an issue). Also, how the priority is specified depends on the function used to set it. Some need the priority to be shifted to the top bits when others don't. This is nearly always the problem with interrupts on Cortex M3 parts.