Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem


Loading

how to support interrupt nested in cpu without NVIC

Posted by zhuchunxia on June 21, 2016

Hi: in my port source file. my interrupt porting code like this define portDISABLEINTERRUPTS() vPortDisableInterrupt() define portENABLEINTERRUPTS() vPortEnableInterrupt() define portSETINTERRUPTMASKFROMISR() GetLocalPSR() define portCLEARINTERRUPTMASKFROMISR(x) SetLocalPSR(x)

GetLocalPSR() will return current interrupt enable flag and disable interrupt SetLocalPSR(x) will store interrupt enable flag by x.

it seems to not support interrupt nested as portSETINTERRUPTMASKFROMISR() disable all interrupt.

should I set mask to those interrupts which is lower than current interrrupt priority to allow higher priority interrupt happen ?

vincent


how to support interrupt nested in cpu without NVIC

Posted by rtel on June 21, 2016

If you are implementing a full interrupt nesting scheme then both taskENTERCRITICAL() and taskENTERCRITICALFROMISR() [also called portSETINTERRUPTMASKFROMISR()] should disable interrupts up to a user defined maximum interrupt priority. The interrupts that have a priority above that maximum will never be disabled by the RTOS, but cannot use the FreeRTOS API.

If you are in a critical section then you don't want interrupts below the user defined maximum to be able to execute - this is not related to interrupt nesting as such as interrupts at or below the above mentioned user defined maximum priority can only nest when you are outside of a critical section (which is the point of entering the critical section).


how to support interrupt nested in cpu without NVIC

Posted by zhuchunxia on June 22, 2016

the user defined maximum interrupt priority you mentioned is configMAXSYSCALLINTERRUPT_PRIORITY ? I know the value is used to set interrupt priority register instead of RTOS kernel . my cpu has no interrupt priority register to rearrange all interrupt prority.


[ Back to the top ]    [ About FreeRTOS ]    [ Privacy ]    [ Sitemap ]    [ ]


Copyright (C) Amazon Web Services, Inc. or its affiliates. All rights reserved.

Latest News

NXP tweet showing LPC5500 (ARMv8-M Cortex-M33) running FreeRTOS.

Meet Richard Barry and learn about running FreeRTOS on RISC-V at FOSDEM 2019

Version 10.1.1 of the FreeRTOS kernel is available for immediate download. MIT licensed.

View a recording of the "OTA Update Security and Reliability" webinar, presented by TI and AWS.


Careers

FreeRTOS and other embedded software careers at AWS.



FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Espressif ESP32

IAR Partner

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Renesas

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

OpenRTOS and SafeRTOS

Xilinx Microblaze and Zynq partner