This is in reference to article titled “Critical Sections” the FreeRTOS web page titled “Running the RTOS on a ARM Cortex-M Core” located at

http://www.freertos.org/RTOS-Cortex-M3-M4.html

There it says:

"BASEPRI is a bit mask. Setting BASEPRI to a value masks all interrupts that have a priority at and (logically) below that value. It is therefore not possible to use BASEPRI to mask interrupts that have a priority of 0."

Thee second statement does not seem to follow precisely from the first. The first part of this paragraph says “priority AT” and the second part says “not possible . . . to mask interrupts that have a priority of 0.” However, the article says priority 0 cannot be masked , so saying “priority at” seems inconsistent. If the article is consistent, a priority of 0 is a logical priority and therefore the highest priority, which is not supposed to be maskable. Is it that the first part the paragraph is true except for logical priority 0?

Please clarify or correct that paragraph for me.

If you want definitive information on how Cortex-M cores work then you will have to refer to the hardware manuals provided by ARM.

As for the paragraph you highlight, I'm struggling to see an inconsistency, so don't fully understand the point you are making.

BASEPRI is a bit mask. Setting BASEPRI to a value masks all interrupts that have a priority at and (logically) below that value.

So, ignoring the confusing bit shifts for a moment and just dealing with logical priorities, if the lowest possible priority is 15 and you set BASEPRI to 10, then "at or logically below" would mean priorities 10, 11, 12, 13, 14 and 15 would be masked. Priority 0, being the highest priority would not be masked.

It is therefore not possible to use BASEPRI to mask interrupts that have a priority of 0

You can write bits into BASEPRI to mask interrupt priorities. As priority 0 does not have any bits set, you cannot write bits into BASEPRI to mask it.

Regards.